
VERILATOR_THREAD_NUM  ?= 8
ifneq ($(VERILATOR_THREAD_NUM),0)
VERILATOR_FLAGS += --threads $(VERILATOR_THREAD_NUM)
# fork and multithreads dump wavs is dangerous, but only one wave is allowed currently
# this just slightly increase the speed of wave dump
VERILATOR_FLAGS += --trace-threads 2
CXXFLAGS += -DVERILATOR_THREAD_NUM=$(VERILATOR_THREAD_NUM)
endif


VERILATOR_FLAGS += $(WAVE_FLAGS)
# Check SystemVerilog assertions
CXXFLAGS_OPTIMIZE += -Os 
VERILATOR_FLAGS += -x-assign 0 -Wno-fatal --assert
VERILATOR_FLAGS += -CFLAGS "$(CXXFLAGS_OPTIMIZE)"
# Generate coverage analysis
#VERILATOR_FLAGS += --coverage
# Run Verilator in debug mode
#VERILATOR_FLAGS += --debug
# Add this trace to get a backtrace in gdb
#VERILATOR_FLAGS += --gdbbt


SIMULATOR_DEF := --top-module soc_top_verilator -Wno-CMPCONST -Wno-fatal 

SIM_FILELIST := -f files.lst

SIM_DUMP := +define+SIM_DUMP

all: sim


VCS_DEFINE += +define+MMU_ON

CASE := simu-kernel


TEST_CASE := ../../../ext/$(CASE)/simu-kernel.bin
TEST_CASE_RAM := testcase_ram.bin

simu:
	@make -C ../../../ext/$(CASE) clean
	@make -C ../../../ext/$(CASE)
	cat $(TEST_CASE) > $(TEST_CASE_RAM)
	../../../scripts/gen_axi_test.py  $(TEST_CASE_RAM)

sim: simu
	verilator -cc --exe $(VERILATOR_FLAGS) $(SIMULATOR_DEF) $(SIMULATOR_LOG) $(SIM_FILELIST) $(SIM_DUMP)
	make -j -C obj_dir -f ../Makefile_obj
	./obj_dir/Vsoc_top_verilator

.PHONY: vmlinux vmlinux.bin

clean:
	rm -rf simv.daidir csrc simv ucli* *.fsdb* obj_dir \
	verdiLog inter.* *.log *.pat *.hex *.img .vcs* \
	*.so *.h stack.info* vmlinux* *exe.report *.bin
